1. Field of the Invention
The present invention relates to a semiconductor memory device technology. More specifically, the present invention relates to nonvolatile memory devices and fabrication method thereof.
2. Description of the Related Art
Flash memory, which is capable of retaining stored data without continued supply of electrical power, has a stacked gate structure of a floating gate and a control gate. The floating gate, which is placed between the control gate and the semiconductor substrate, is isolated by an insulating oxide layer. The flash memory device is classified, according to its cell array structure, into two classifications: NOR flash and NAND flash. The NAND flash has higher integration and is suitable for use in electronic devices requiring high storage capacity. The NOR flash memory allows higher speed and random access to the memory cells but it requires a space for the each of memory cells being interconnected to a bit line and has relatively low integrity.
The NOR flash memory devices have a plurality of memory cells arrayed in row and column directions. Memory cells placed in row direction are connected in parallel to a bit line, while memory cells placed in column direction are connected in parallel to a word line. When memory cells connected to non-selected word line are over-erased, current may flow through the bit line regardless of which memory cells are selected or activated. As a result, all of the memory cells connected to the selected bit lines are erroneously recognized as turned-on cells.
In flash memory device, split gate type device has a word line that overlaps in part the floating gate and functions as both selection gate and control gate.
FIG. 1 is a cross-sectional view of the conventional split gate flash memory cells.
Referring to FIG. 1, drain region 24 is formed in a semiconductor substrate 10. At both sides of the drain region 24, floating gates 12 are formed on tunnel oxides 18 on the substrate 10. The memory cells are formed in active region electrically separated by isolation regions (not shown). On the floating gate 12, gate poly insulating layer 14 having elliptic section is formed and thus sharp edges or tips are present at the edges of the floating gate.
In the active regions, source regions 22 are formed apart from the floating gate 12. Portion of the substrate placed between the source regions 22 and the floating gate and the word line 16 overlying the floating gate overlap. The word line 16 is disposed to come across the isolation layer. Insulating layers 20 are formed between the word line 16 and floating gate 12 and between the word line 16 and active regions.
In a write or programming operation of the split gate flash memory device, the word line 16 overlapping the active regions acts as the gate electrode of a selection transistor to make the channel in the active regions turned-on, and electrons are injected into the floating gate 12 through the tunnel oxide 18 by the capacitive coupling of the floating gate 12 when a predetermined voltage is applied to the drain region 24. In an erase operation of the split gate flash memory device, when an erase voltage is applied to the word line 16, electric charges injected into the floating gate are erased through the tips of the floating gate 12.
With this structure of word line overlapping the portion of active region between the floating gate 12 and the source region 22, turning-on of the memory cells connected to a bit line cannot be detected so long as over-erased memory cells have their selection transistors turned-on, even when the over-erased memory cells share a common bit line.
In spite of this advantage, the conventional split gate flash memory devices have defects in that misalignment of the word line relative to the active region and the floating gate causes variations of transistor characteristics. When the overlapping area of the word line and floating gate varies, the coupling ratio of the cell transistors is changed, and when the overlapping area of the word line and the active region varies, the threshold voltage of the selection transistor is changed.
Further, like the NOR type flash memory device, the split gate flash memory reveals the limitation in increasing integration because the memory cells are fabricated in active regions defined by isolation layers. Moreover, the gate oxide or tunnel oxide is made thinner at interfaces between the isolation layers and the active regions.